Computer Architecture Techniques for Power-Efficiency
Estimated delivery business days. Format Paperback. Condition Brand New. Description Documents some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems.
Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Switching to chip multiprocessors reduces the effect of wire delays the length of time it takes a signal—output from a gate—to travel along a given length of wire , which is growing relative to the gate delay the length of time it takes to translate input to a logic gate to be transformed into output from that gate.
Interprocessor communication still requires long wires, but the latency of interprocessor communication is less critical for performance in a CMP system than is the latency between units within a single processor. In addition, the long wires can be pipelined and thus do not affect the clock-cycle time and performance of individual processors in a CMP. Chip multiprocessors are a promising approach to scaling, but they face challenges as well; problems with modern scaling are described in the next section. Moreover, they cannot be programmed with the techniques that have proved successful for single processors; to achieve the potential performance of CMP, new software approaches and ultimately parallel applications must be developed.
This will be discussed in the next chapter. If voltages could continue to be scaled with feature size following classic Dennard scaling , CMP performance could continue to be scaled with technology. However, early in this decade scaling ran into some fundamental limits that make it impossible to continue along that path, 26 and the improvements in both performance and power achieved with technology scaling have slowed from their historical rates. The net result is that even CMPs will run into power limitations. To understand those issues and their ramifications, we need to revisit technology scaling and look at one aspect of transistor performance that we ignored before: leakage current.
As described earlier, CMOS circuits have the important property that they dissipate energy only when a node changes value. When its input is low V gnd , it turns on, connects V supply to the output, and drives the output high to V supply. The other type of CMOS device, an nMOS transistor, has the complementary behavior: when its input is high V supply , it connects the output to V gnd ; when its input is low V gnd , it disconnects the output from V gnd. Hence, the only current that flows through the gate is that needed to charge or discharge the capacitances associated with the gate, so the energy consumed is mostly the energy needed to change the voltage on a capacitor with transistors, which is C load multiplied by V supply 2.
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For that analysis to hold, it is important that the off transistors not conduct any current in the off state: that is, they should have low leakage. However, the voltage scaling that the industry has been following has indirectly been increasing leakage current. Transistors operate by changing the height of an energy barrier to modulate the number of carriers that can flow across them.
The actual situation is more complex. The basic reason is related to thermodynamics.
At any finite temperature, although. The probability of having an energy higher than the average falls off exponentially, with a characteristic scale factor that is proportional to the temperature of the transistors measured measured in kelvins.
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The hotter the device, the wider the range of energies that the carriers can have. That energy distribution is critical in the building of transistors. Even with an energy barrier that is higher than the average energy of the carriers, some carriers will flow over the barrier and through the transistor; the transistor will continue to conduct some current when we would like it to be off.
The energy scale is kT, where k is the Boltzmann constant and T is the temperature in kelvins. Thus, the current through an off transistor drops exponentially with the height of the energy barrier, falling by slightly less than a factor of 3 for each mV increase in the barrier height.
The height of the barrier is normally called the threshold voltage V th of the transistor, and the leakage current can be written as. The leakage current increases by about a factor of 10 each time the threshold voltage drops by another mV. Historically, V th s were around mV, so the residual transistor leakage currents were so small that they did not matter. Starting from high V th values, it was possible to scale V th , V supply , and L together.
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While leakage current grew exponentially with shrinking V th , the contribution of subthreshold leakage to the overall power was negligible as long as V th values were still relatively large. But ultimately by the nm node, the leakage grew to a point where it started to affect overall chip power. One approach to reduce leakage current is to reduce temperature, inasmuch as this makes the exponential slope steeper.
That is possible and has been tried on occasion, but it runs into two problems. The first is that one needs to consider the power and cost of providing a low-temperature environment, which usually dwarf the gains provided by the system; this is especially true for small or middle-size systems that operate in an office or home environment. The second is related to testing, repair, thermal cycling, and reliability of the systems.
For those reasons, we will not consider this option further in the present report. However, for sufficiently large computing centers, it may prove advantageous to use liquid cooling or other chilling approaches where the energy costs of operating the semiconductor hardware in a low-temperature environment do not outweigh the performance gains, and hence energy savings, that are possible in such an environment. V th stopped scaling because of increasing leakage currents, and V supply scaling slowed to preserve transistor speed with a constant V supply — V th.
Once leakage becomes important, an interesting optimization between V supply and V th is possible. Increasing V th decreases leakage current but also makes the gates slower because the number of carriers that can flow through a transistor is roughly proportional to the decreasing V supply — V th. One can recover the lost speed by increasing V supply , but this also increases the power consumed to switch the gate dynamically.
For a given gate delay, the lowest-power solution is one in which the marginal energy cost of increasing V dd is exactly balanced by the marginal energy savings. The balance occurs when the static leakage power is roughly 30 percent of the dynamic power dissipation. This leakage-constrained scaling began at roughly the nm technology node, and today both V supply and V th scaling have dramatically slowed; this has also changed how gate energy and speed scale with technology.
Clearly, that is not optimal, so many designers are scaling V dd slightly to increase the energy savings.
That works but lowers the gate speeds, so some parallelism is needed just to recover from the slowing single-thread performance. The poor scaling will eventually limit the performance of CMPs. Combining the lessons of the last several sections of this chapter, the committee concluded that neither CMOS nor chip multiprocessors can overcome the power limits facing modern computer systems. That leads to another core conclusion of this report.
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Basic laws of physics and constraints on chip design mean that the growth in the performance of computer systems will become limited by their power and thermal requirements within the next decade. Optimists might hope that new technologies and new research could overcome that limitation and allow hardware to continue to drive future performance scaling akin to what we have seen with single-thread performance, but there are reasons for caution, as described in the next section. Finding: The growth in the performance of computing systems—even if they are multiple-processor parallel systems—will become limited by power consumption within a decade.
The answer to the question is mixed. Recent press reports make it clear, for example, that Intel expects to be using silicon supplemented with other materials in future generations of chips. A recent study compared estimated gate speed and energy of transistors built with exotic materials that should have very high performance. Those results should not be surprising. The fundamental problem is that V th does not scale, so it is hard to scale the supply voltage.
The limitation on V th is set by leakage of carriers over an energy barrier, so any device that modulates current by changing an energy barrier should have similar limitations. All the devices used in the study cited above used the same current-control method, as do transistors made from nanotubes, nanowires, graphene, and so on. A few options are being pursued, but each has serious issues that would need to be overcome before they could become practical. One alternative approach is to stop using an energy barrier to control current flow and instead use quantum mechanical tunneling.
That approach eliminates the problem with the energy tails by using carriers that are constrained by the energy bands in the silicon, which have fixed levels. Because there is no energy tail, they can have, in theory, a steep turnon characteristic. Many researchers are trying to create a useful device of this type, but there are a number of challenges.
The first is to create a large enough current ratio in a small enough voltage range. The tunneling current will turn on rapidly, but its increase with voltage is not that rapid. Even if one can create a device with that current ratio, another problem arises.https://phimagchyuni.tk
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The speed of the gates depends on the transistor current. So not only do we need the current ratio, we also need devices that can supply roughly the same magnitude of current as CMOS transistors provide. Tunnel currents are often small, so best estimates indicate that tunnel FETs might be much slower less current than in CMOS transistors. Such slowness will make their adoption difficult. Another group of researchers are trying to leverage the collective effort of many particles together to get around the voltage limits of CMOS.
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Recall that the operating voltage is set by the thermal energy kT divided by the charge on one electron, because that is the charged particle. If the charged particle had a charge of 2q, the voltage requirements would be half what it is today. That is the approach that nerve cells use to operate robustly at low voltages.
The proteins in the voltage-activated ion channels have a charge that allows them to operate easily at mV. Although some groups have been trying to create paired charge carriers, most are looking at other types of cooperative processes.
The ion channels in nerves go though a physical change, so many groups are trying to build logic from nanorelays nanomicroelectromechanical systems, or nano MEMS. Because of the large number of charges on the gate electrode and the positive feedback intrinsic in electrostatic devices, it is theoretically possible to have very low operating voltages; indeed, operation down to a couple of tenths of a volt seems possible.
Even as researchers work to overcome that hurdle, there are a number of issues that need to be addressed. The most important is determining the minimum operating voltage that can reliably overcome contact sticking. It might not take much voltage to create a contact, but if the two surfaces that connect stick together either because of molecular forces or because of microwelding from the current flow , larger voltages will be needed to break the contact.